Parity-Check-CRC Concatenated Polar Codes SSCFlip Decoder

Successive cancellation flip decoding requires a large number of extra successive attempts at low signal-to-noise ratios (SNRs), resulting in high complexity. In addition, it has long latency. Although modifications have been proposed decoding, these still computational complexity SNRs due to huge additional attempts. It is desirable detect the unsuccessful process an early stage and stop that can reduce This paper combines parity-check-CRC concatenated polar codes with low-latency simplified proposes (PC-CRC-SSCFlip) decoder. further employs parity-check vector identify terminates so minimize on average. Additionally, this work error-prone flipping list by incorporating empirically observed indices based channel-induced error distribution along first bit each Rate-1 node. The technique more than one through correct them. narrows down search space for identification erroneous decisions. Simulation results show 60% terminate rather decode whole codeword. PC-CRC-SSCFlip decoder approximately 0.7 dB 0.3 gains over decoders, respectively, fixed block rate (BLER) = 10−3. reduces average latency low-to-medium while approaching medium-to-high SNRs.